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enhanced calling line identifier with call waiting KS8630d 1 preliminary brief description KS8630d is a low power mixed signal cmos integrated circuit for receiving a physical layer signals used in the calling line identification presentation (clip) of british telecom system, the calling identity delivery(cid) of bellcore system, and similar evolving systems before the call is put through. it can also satisfy the requirements of cidcw (calling identity delivery on call waiting) services including very high precision detection of cas (cpe alerting signal) tone and the signals used in similar services when the call has already been put through. KS8630d carries out the following features : ring or line-reversal detection, cas ( 2130hz and 2750hz) tone detection, and 1200-baud fsk demodulation which simultanesouly satisfies the bell202 and the ccitt ( itu-t ) v.23 specification. the demodulated data for caller identification is transmitted serially to the related u-controller. KS8630d using a patented digital algorithm to detect demodulated fsk signals and cas signal detection. the device also has a built-in automatic gain control circuitry which is capable of very high precision detection of cas tone. it is suitable for use in adjunct boxes or feature phones with cid / cidcw applications. f eatur es ? cid and cidcw system operation ? high performance cas detection and loop state tone alert signal detection ? internal automatic gain control circuitry for the high precision cas detection ? digital logic fsk demodulator ? ring or line-polarity reversal detection ? low power consumption in standby mode ? 3.58mhz crystal oscillator ? 3.3v ~ 5v operation ? 16-sop package ( 225mil ) applications ? cid / cidcw adjunct boxes and feature phones ? a system for british telecom, bellcore, cca ? computer telephone integrated system ? call logging systems ? voice-mail equipment ordering information device package operating temperature KS8630 16-sop-225 0 c ~ 70 c 16-sop-225
KS8630d enhanced calling line identifier with call waiting 2 preliminary block diagram figure 1. KS8630d block diagram bpf bpf bpf lpf lpf agc adc gain control 8 5 peak detector level detector fsk demodulator tone discriminator mode & interrupt generator rd inp inn rtb dclk data mode intb bias generator voltage sensing block oscillator & clock gen xin xout pd vref agc_vb offhook to/from microcontroller
enhanced calling line identifier with call waiting KS8630d 3 preliminary pin diagram figure 2. KS8630d pin diagram 1 2 16 3 4 5 6 7 8 15 14 13 12 11 10 9 KS8630d v dd agc_vb i nn i np v ref rd rtb pd xout xin intb dclk offhook mode data v ss
KS8630d enhanced calling line identifier with call waiting 4 preliminary pin description pin no. pin name type description 1 v dd p positive power supply. 2 agc_vb o agc block bias terminal. usually a 0.47uf capacitor is connected between this pin and v ref pin to reduce a dc offset produced by internal circuitry. 3 i nn i inverting input of the on-chip input signal amplifier. 4 i np i non-inverting input of the on-chip input signal amplifier. 5 v ref o reference voltage. typically 0.1 ~ 1uf is connected to gnd. 6 rd i(s) schmitt trigger input to detect the ringing signal, ring-burst signal, line-polarity reversal signal. 7 rtb i(s)/o open drain output/schmitt trigger input. an external resistor to v dd and a capacitor to v ss should be connected with rtb to filter and to extend the rd input signal. each components value is related to the schmitt trigger input threshold and input signal frequency. 8 pd i(s) power down. schmitt trigger & voltage sensing input. if set to high level, all circuitry goes to power down mode except ring detection & mode selection block. in order to satisfy the bt or bellcore specification, it is recommended to add a different application circuits. all digital block can be resetted by this pin control. whenever the u-controller unmutes handset and enables keypad in off-hook state, KS8630d must receive a reset pulse by this pin from microcontroller. 9 v ss p negative power supply. 10 data b demodulated fsk data output. default state is a logic high level. data is tranmitted serially to the microcontroller ( 8bit /unit, lsb first ). dclk is used for sync clock of this data. in case of using this pin as input, it is used for testing of KS8630d functionality. 11 mode b mode output signal to show the current status ( ring / dual tone / fsk signal receiving). default state is a logic high level. if detects a cas tone, this mode pin will be set to logic low level during a pre- determined timming. if detects a ring or fsk signal, this pin will be set to high level. with the intb pin, it can be informed current status to microcontroller. in case of using this pin as input, it is used for testing of KS8630d functionality. 12 offhook i hook status input. if set to high level, the operation condition of KS8630d go to the off-hook state. if set to low level, it goes to the on-hook state. 13 dclk b synchronous clock output of data. default state is logic high level. the right data is in falling edge of this clock. in case of using this pin as input, it is used for testing of KS8630d functionality
enhanced calling line identifier with call waiting KS8630d 5 preliminary notes: i = input i(s) = schmitt trigger input o = output b = bidirectional i/o 14 intb o interrupt output signal. it is an active low output that may be used as an interrupt request / wake-up signal to the microcontroller. in case of ringing or line polarity reversal detection, dual tone detection and the mark signal detection of fsk data, it will be activated. with the mode pin, it indicates current status to the microcontroller. 15 xin i the input of the 3.58mhz on-chip crystal oscillator inverter. 16 xout o the output to the 3.58mhz on-chip crystal oscillator inverter. pin description (continued) pin no. pin name type description
KS8630d enhanced calling line identifier with call waiting 6 preliminary typical application circuit figure 3. recommended typical application circuit components notes: 1. when applying to the bt system, change r10 to 330k w to detect the line reversal signal. 2. when applying to the bt system, insert a resistance between the mcu ? s pd related pin and KS8630d pd pin (refer to section 1.6). r1, r2, r3 470k w c1, c2 10pf r4 150k w c3, c4 22nf r5, r6, r7, r8 100k w c5 10 m f r9 82k w c6, c7, c8 100nf r10 56k w c9 0.47 m f (note 1) c10 220nf r11 47k w (note 2.) c11 0.1 m f x1 3.579545mhz d1, d2, d3, d4 1n4004 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 KS8630d vdd pd vdd tip ring vdd xout xin intb dclk offhook mode data vss rtb rd vref inp inn agc_vb vdd r8 r7 c9 r4 c10 r10 c11 c1 c2 r11 r9 d1 d2 d3 d4 r1 r2 c7 c8 c3 c4 r5 r6 c6 c5 to/from microcontroller note 1 note 2 x1 r3
enhanced calling line identifier with call waiting KS8630d 7 preliminary general description KS8630d is suitable for use in both system to british telecom specificatios and bellcore specifications. KS8630d to be used in different systems, the predetermined signals must be applied to the pd (pin#8) and the offhook ( pin#12), which are defined by the application circuits or the microcontroller. all detection modes related to the pd pin and the offhook pin are listed below: notes: 1. if a false reponse (talk-off) occurs or microcontroller receives fsk data, microcontroller should send low edge pulse (with 10us duration timming approximately) to the pd pin. then, KS8630d will be re-initialized to the dual tone(cas) detection mode. 2. if KS8630d is used in the bellcore system, a pull-up resistor should be inserted between the pd pin and v dd . 3. if KS8630d is used in the bt system, a pull-up resistor should be inserted between the pd pin and v dd . in this case, a resistor should be inserted between KS8630d ? s pd pin and microcontroller ? s pd related pin. then, the voltage level of KS8630d ? s pd pin will be 1/3*v dd when microcontroller's pd related pin set to low state. pd offhook detection mode (note1) remark l l fsk demodulation bellcore system (note2) l h dual tone detection ? fsk demodulation 1/3 * v dd l dual tone detection ? fsk demodulation bt system (note3) 1/3 * v dd h dual tone detection ? fsk demodulation h l ringing or line reversal detection h h - table 1. a status of each detection mode
KS8630d enhanced calling line identifier with call waiting 8 preliminary functional description ring or line reversal detector it can be detected the ringing signal or the line polarity reversal signal as in the clip, cid, and cds protocols. the signals between tip and ring block pass through the bridge circuitry and the rectified signal is input to the rd (pin #6). if the rectified signal is larger than the internal threshold v th , the rtb block stays in the low level while the signal is maintained by the external resistor and capacitor . for the line polarity reversal detection, the logic low level section within rtb block is also decided by the external resistor and capacitor value. when a ringing or a line polarity reversal signal is detected, an active low pulse is outputted by the interrupt generator to the intb (pin#14) . figure 4. ring or line reversal detector figure 5. signals of ring detection tip ring r10 d1 d2 d3 d4 r1 r2 c7 c8 r3 vdd rd rtb KS8630 r4 c10 interrupt generator intb tip/ring rd rtb intb v th v th vss vss
enhanced calling line identifier with call waiting KS8630d 9 preliminary figure 6. signals of line reversal detection tip/ring rtb intb v th
KS8630d enhanced calling line identifier with call waiting 10 preliminary input signal amplifier KS8630d can adjust the input signals appearing at the tip/ring block in application, so that they are included within the range that can be handled with the block. the internal amp. configuration of KS8630d is a subtract structure, and it was recommend that the signal input in the differential mode to the chip is reduced by half level compared to the signal in the tip/ring block. figure 7. input signal amplifier. (a) single-ended (b) differential-ended filtering block the outband noise of input signal which interfered by transmission line or near-end speech is eliminated by the filtering block. the filtering block includes the scf-configured dual tone bpf, fsk bpf, and lpf for filtering the scf clock-generated noise. the dual tone bpf is a narrowband 4th filter which composed of biquads. the quality factor of dual tone filter is between 20 and 25 approximately. the low tone filter and high tone filter are composed of same core, and the cutoff frequency can be changed according to the switching clock (clk1, clk2). the fsk bpf is a wideband 4th filter, and the dual tone bpf and fsk bpf can be selected according to the detection mode in KS8630d . (a) (b) vref inp inn r2 c1 r r r r amplifier vref inp inn r8 r7 c3 c4 r5 r6 r r r r amplifier
enhanced calling line identifier with call waiting KS8630d 11 preliminary figure 8. filtering block figure 9. bpf characteristics (a) low tone filter (b) high tone filter (c) fsk filter bpf bpf bpf lpf lpf input signal clk1 clk1 clk2 output signal -30 -25 -20 -15 -10 -5 100 10k freq[hz] volt[lin] 0 1k (a) (b) (c) -50 -40 -30 -20 -10 0 0 1k 2k 3k 4k 5k freq[hz] volt[lin] -50 -40 -30 -20 -10 0 0 1k 2k 3k 4k 5k freq[hz] volt[lin]
KS8630d enhanced calling line identifier with call waiting 12 preliminary automatic gain control this block controls the agc amplifier gain using the adc output signal, so that the cas detection and the fsk demodulation block can be operated within an adequate dynamic range, and the adc output can have enough resolution. connect a ?coff ? between agc_vb and v ref to eliminate the amplification of dc offset. figure 10. automatic gain control block the range of input signals for agc operation is about 35db, and the gain of the input signal has an hysteresis characteristics. if a signal which is larger than 7/8 of the adc input dynamic range is input into the adc, the gain is immediately decreased. if a signal which is smaller than 1/4 of the adc input dynamic range is continuously input for more than a set amount of the time (about 2ms), the gain is immediately increased. the adc input dynamic range is about 2v. figure 11. figure 9. input signal vs. gain agc adc gain control 8 5 agc_vb filter_out c off vref d i r e c t i o n o f g a i n d e c r e a s e d i r e c t i o n o f g a i n i n c r e a s e
enhanced calling line identifier with call waiting KS8630d 13 preliminary dual tone alerting signal detection (cas signal detection) the 2130hz and 2750hz components that are output from each bpf are synthesized, converted into am waveform, and used as the analog input to the 8-bit adc. the synthesized analog signal is converted into digital data through the adc and in the given sampling rate. use this data to find the highest peak (mxb) of the 2440hz component (frequency sum). also, use this mxb to find the highest peak (pk) and lowest peak (bmn) of the 620hz component (frequency difference). carrier signal : (2750 + 2130) / 2 = 2440hz ? frequency sum envelope signal : (2750 - 2130) / 2 = 310hz ? frequency difference figure 12. adc input signal waveform and calculated peak position the pk error correction algorithm was applied in KS8630d to reduce the pseudo pk signal generation (from voice noise) as much as possible. pk signals occur in a 620hz period as shown in fig 12. since the pk occurs regularly for a cas signal, you can eliminate the pseudo pk using this characteristic. the corrected pk is used to carry out the cas detection algorithm. first comes the cas_seek block operation that checks whethere there is cas within the channel. this block uses the fact that mxb and pk signals occur within a specific range when cas is being transmitted. after the cas signal has started the transmission, the gain control is carried out. while the adc input is maintained at a specific gain, it takes about 5ms to generate a casis signal. the cas detection algorithm is carried out immediately when casis becomes high. it takes about 58ms after casis becomes high to detect any cas. mxb pk bmn carrier signal (2440hz) envelope signal (310hz)
KS8630d enhanced calling line identifier with call waiting 14 preliminary figure 13. dual tone alerting signal(cas) detection flowchart 1. find the average value of the pk generation period from the envelope component, and check if it enters into a specific margin. 2. use am waveform characteristics to check if the difference in the bmn level near pk exceeds specific conditions. 3. check if each pk ? s interval is within specific conditions. cas_seek block detects cas like signal(casis)? cas detection algorithm is executed no yes 58ms is elasped? no pre_cas is high? yes no yes length_chk block is executed casis falling edge goes low ? pre_cas's high time is smalled than 22.5ms? yes no cas is detected !!! yes cas is not detected ! no start
enhanced calling line identifier with call waiting KS8630d 15 preliminary about 58ms after the casis becomes high, check whethere all the above conditions are fulfilled, and if they are, generate the pre_cas signal which signifies that there is cas. if the pre_cas set to high as shown in fig. 13, the length_chk block starts its operations. the pseudo cas is rejected by using the fact that cas ? s off-hook transmission is between 75ms ~ 85ms. if the pre_cas ? s high duration is less than 22.5ms, cas detection will be carried out successfully. KS8630d ? s cas detection uses the method of checking the sine wave ? s characteristics while the adc input gain is regularly maintained, or uses the fact that the cas signal ? s transmission duration is always the same. even when casis becomes high, if the gain changes or it becomes known that it isn ? t a different cas, KS8630d comes out of the cas detection algorithm at once to prevent talk-off counting . also, to prevent talk-down, we use an error correction algorithm that restores the sine wave?s characteristics that have been distorted by voice noise, as much as possible. figure 14. dual tone alerting signal(cas) detection timing if cas is detected after the cas signal has started transmission and the algorithm of fig 13. are all executed, it should alert to the mcu using the mode output and the intb output. fig 14. shows the timing of mode and intb operation. after detecting that the cas transmission is over, mode after t amode is enabled to low, and the intb is sent to the mcu after this, the mcu expects fsk data from KS8630d and waits for it. fsk demodulation KS8630d uses own digital fsk demodulation algorithm. the analog signal that has passed through the bpf which has frequency band of fsk signal goes through the adc and it is digitally converted in the specified sampling rate. same as the dual tone alerting signal detection, the signal ? s highest peak detecting algorithm is applied for finding each frequency components ? peak. the interval information of the peaks are used to decide if the fsk data being transmitted is mark bit( ? 1 ? ) or space bit( ? 0 ? ). although the bellcore standards and bt ? s fsk signal components are different, KS8630d raised circuit efficiency by using an fsk demodulation algorithm that satisfies both standards in the same circuit. when a mark signal (normally, a continous mark bit( ? 1 ? ) of minimum 58bits is transmitted) is found in the fsk data being transmitted, the intb signal is sent to mcu to tell it that the fsk data transmission will soon occur. when the mark signal ends and caller information is sent starting at the start bit, it is sent to mcu through the data, dclk output. dual tone alert signal line signal mode intb t amode t moded t mint t intd
KS8630d enhanced calling line identifier with call waiting 16 preliminary figure 15. fsk demodulator operation timing (on-hook) data retiming KS8630d uses two pins to send fsk data to mcu. data sends the demodulated fsk data, and dclk transmits the clock synchronous to data. figure 16. data and dclk generation timing channel seizure mark signal fsk data line signal intb t mkint t intd2 start bit start bit stop bit stop bit start bit dummy mark bit(n bit) mark signal b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 line signal data dclk "10101010" "10101010" "101" t dclk
enhanced calling line identifier with call waiting KS8630d 17 preliminary application notes on-hook operation on-hook means that the telephone set is not being used. in the on-hook state, the caller id information will be displayed on the lcd pannel before you answer the call. bt(british telecom) system in the on-hook state, the bt protocol sends an ?idle state tone alerting signal? by means of monitoring the input signal level. for more detailed specification, please refer to british telecom's sin227, and sin242. figure 17. british telecom on-hook system signals [1] : sum of two periods may not exceed 5 sec. [2] : typically 500ms [3] : please refer to fig 16. tone alert channel seizure mark message line reversal 100ms 88~110ms 45ms 80~262ms 45~72ms 2.5sec >200ms ringing call arrival indication signal line signal rd rtb mode intb t intd1 t amode t moded t mint t mkint pd t intpd t msgpd data dclk clock t intd2 t intd2 data
KS8630d enhanced calling line identifier with call waiting 18 preliminary the 2130hz and 2750hz components of the tone alert signal are transmitted simultaneously and the ? 10 ? is continously repeated for the channel seizure signal. the mark signal is composed of continuous ? 1 ? , and the message is consists of the start bit ( ? 0 ? ), 8-bit real data, stop bit ( ? 1 ? ) and inserted dummy mark bit (0~20 bit). a low edge pulse is generated into the intb pin if KS8630d detects a line polarity reversal. then the microcontroller must detect this signal and put the pd pin into the low state level. must be careful when the microcontroller detects the end of fsk data or if the fsk data is not detected during the set amount of time , so that the pd (pin # 8) of KS8630d becomes re-initialized back to power down mode ( high state). bellcore system in the on-hook state, the bellcore protocol does not send the dual tone cpe alerting signal. for more detailed information, please refer to bellcore specification : gr-30-core, and sr-tsv-002476. figure 18. bellcore on-hook system signals for the channel seizure signal, the ? 10 ? is continously repeated. the mark signal is composed of continuous ? 1 ? , and the message is consists of the start bit ( ? 0 ? ), 8-bit data, stop bit ( ? 1 ? ) and inserted dummy mark bit (0~20 bit). when KS8630d detects the end of ringing signal, the intb ( pin # 14) generates a low edge pulse. the microcontroller detects this signal and sets the pd( pin # 8) to low state level. must be careful when the microcontroller detects the end of fsk data or if fsk data is not detected during the set amount of time (approximately 500ms), so that that the KS8630d ? s pd( pin # 8) becomes re-initialized back to power down mode (high state). 1'st ring channel seizure mark message typically 2sec 250ms 150ms 2'nd ring line signal rd rtb intb t intd1 t mkint pd 250~500ms 200ms max 2.9~3.7sec t intpd t msgpd data dclk clock t intd2 data
enhanced calling line identifier with call waiting KS8630d 19 preliminary off-hook operation off-hook means that the telephone set is currently being used. the cidcw (calling identity on call waiting) service means displaying a different caller?s identity on the lcd pannel while still on the line with another call. since the telephone set is being used, the operator must send a cas (cpe alerting signal) before sending the caller id information, to initialize the cidcw service. the performance of subscriber?s phone (cpe) is a error rate of the cas signal detection when the speech signal interfered as a noise. if talk-down (missing cas) occurs, the caller id information can be lost, and if talk-off (false response) occurs, the caller at the far end will hear unwanted noise. cas is transmitted in the same frequency band as the voice signals, so that the talk-off and the talk-down performance is very important to decide the efficiency of caller id system. KS8630d uses the bpf and patented digital detection algorithm to detect the dual tone cpe alerting signal, so it is possible to minimize the talk-off and the talk-down error ratio. bt (british telecom) system figure 19. KS8630d's timing diagram in bt, off-hook status if the talk-off occurs, or if the microcontroller has finished transmitting fsk data, a high state pulse must be transmitted to the pd ( pin # 8 ) to re-initialize the KS8630d same as fig 19. tone alert mark network start point 40~50ms silence 80~85ms ack 100ms 65~75ms 5~100ms detect alert signal disable speech path send ack network speech path restored within 100ms silence if no message detected, restore speech path terminal equipment waiting for ack signal detect ack signal mode pd message 45~75ms intb t moded t amode t mint t mkint t msgpd t pd w data clock dclk t intd2 t intd2 data
KS8630d enhanced calling line identifier with call waiting 20 preliminary bellcore system off-hook state data tranmission of bellcore system is similar to the british telecom system, but there is a difference in timming. figure 20. (d). KS8630d ? s timing diagram in bellcore, off-hook status if the talk-off occurs, or if the microcontroller has finished transmitting fsk data, a high state pulse must be transmitted to the pd ( pin # 8 ) to re-initialize the KS8630d same as fig 20. cas data network cpe goes off-hook 75~85ms ack 100ms 65~75ms 5~100ms send ack cpe unmutes handset & enables keypad cpe cpe mute handset &disables keypad mark 58~75ms 50ms pd t moded t amode t mint t mkint t msgpd t pd w mode intb data dclk clock t intd2 t intd2 data
enhanced calling line identifier with call waiting KS8630d 21 preliminary absolute maximum ratings (t a = 25 c) characteristic symbol value unit supply voltage v dd 0.3 ~ 6.0 v power dissipation p d 500 mw operating temperature t opr 0 ~ 70 c storage temperature t stg - 65 ~ 150 c electrical characteristics (ta = 25 c, v dd = 3.3v, unless otherwise specified) characteristics symbol min. typ. max. unit dc characteristics operating voltage v dd 3.0 - 5.5 v operating current i dd - - 5 ma schmitt input high threshold(rd) v thr 0.75*v dd - - v schmitt input low threshold(rd) v tlr - - 0.25*v dd v schmitt input high threshold(pd) v thp 0.70*v dd - - v schmitt input low threshold(pd) v tlp - - 0.5*v dd v ac electrical characteristics cas, idle state alerting tone detection acceptance range cas ar ( 0.5%) 2120 2130 2140 hz 2737 2750 2763 hz rejection range cas rr <2055 - >2205 hz <2653 - >2847 hz acceptance signal level per tone cas asl -40 - -2 dbv [note1] reject signal level per tone cas rsl - - -46 positive and negative twist detect cas td - - 6 db[note2] fsk detection transmission rate 1188 1200 1212 baud bell202 mark("1") 1188 1200 1212 hz bell202 space("0") 2178 2200 2222 hz v.23 mark("1") 1280 1300 1320 hz v.23 space("0") 2068 2100 2132 hz
KS8630d enhanced calling line identifier with call waiting 22 preliminary notes: 1. dbv: decibels above or below a reference voltage of 1 vrms signal level is per tone. 2. db: twist = 20 log (f h amplitude / f l amplitude) 3. dbv: decibels above or below a reference voltage of 1 vrms. cf) dbm : decibels above or below a reference power of 1mw into 600 w . 0dbm = 0.7746vrms. 4. these times are required by the microcontroller. for KS8630d to work properly, these timings must be observed. input level detection fsk ld -40.0 - -3.0 dbv [note3] acceptable twist level fsk at - - 6 db signal timing specification cas, idle state alerting tone detection end of tone alert signal to mode low timing t amode 1.7 2.0 10 ms mode low to int low timing t mint 200 250 300 us mode low duration timing t moded 15 18 20 ms int low duration timing when ring / line reversal occurs t intd1 same timing width as ring / line-reversal detection at tip / ring. refer to fig 5 / fig 6 timing int low duration timing t intd2 1.5 1.7 2.0 ms fsk detection mark signal start time to int low timing t mkint 26 27 35 ms dclk's low duration time t dclk 60 70 80 us 1st intb to pd low time in on-hook state t intpd [note4] 1 5 10 ms message end to pd high time t msgpd [note4] 1 5 10 ms pd high pulse width in off-hook state t pdw [note4] 30 50 100 us electrical characteristics (continued) (ta = 25 c, v dd = 3.3v, unless otherwise specified) characteristics symbol min. typ. max. unit
enhanced calling line identifier with call waiting KS8630d 23 preliminary package dimension a: 6.00 0.30 / 0.236 0.012 b: 3.95 0.20 / 0.156 0.008 c: 5.72 / 0.225 d: 0 ~ 8 e: 0.20 + 0.10, -0.05 / 0.008 + 0.004, - 0.002 f: 0.60 0.20 / 0.024 0.008 g: 10.30 max / 0.405 max h: 9.90 / 0.390 i: 0.51 / 0.020 j: 0.41 0.10 / 0.016 0.004 k: 1.27 / 0.050 l: 0.05 min / 0.002 min m: 1.55 0.20 / 0.061 0.008 n: 1.95 max / 0.077 max a #1 #8 #9 #16 b c d e f g h i j k l m n 0.10 max 0.004 max

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